The present disclosure relates to semiconductor device design, manufacture and packaging methods to improve electrical current delivery into a semiconductor chip.
Flip chip generally uses the Controlled Collapse Chip Connection or, C4, technology to interconnect semiconductor devices of IC chips or Microelectromechanical systems (MEMS), or alternatively, the chip die, to packages for connection to external circuitry with solder bumps that have been deposited onto the chip pads. Power has to be delivered to die from package through these C4 bumps. There is a limit as to how much current each C4 bump can carry. This limit must be managed.
The C4 current limit is set by the target electromigration lifetime governed by several key factors. As shown in FIG. 1, key factors 10 that effect C4 lifetime electromigration reliability 11 include: C4 technologies 12 (e.g., lead-free, design structure/mechanics, pad shape/structure); C4 operating currents 14, and C4 operating temperatures 16—all which effect electromigration reliability of the chip over time. Factors effecting C4 operating currents include the amount of current drawn by integrated circuit devices 14a on the chip or die, the density and location of the C4 bumps 14c, and the power grid networks 14b that connect the devices and the C4 bumps. That is, the power dissipated or current drawn by the devices is delivered from the package pins through substrate wires therein through the C4 connections to distribute current to the chip die through one or multiple chip wiring levels. Thus, current delivery design factors include the amount of current drawn by and the location of operating devices at the die, how they are wired (designed power grid between C4s and devices), and how many C4s are populated in a unit area and how they are placed, all effect C4 current draw and ultimately chip reliability susceptible to electromigration.
In semiconductor chip manufacturing, C4 current limits are becoming difficult to meet due to a variety of factors including: increasing use of Pb-free C4; higher target frequencies of IC chip operation; and frequency boosted modes of operation. It would be highly desirable to provide a current-aware floorplanning semiconductor chip design mechanisms to manage current draw through C4 connectors. However, there are currently no known automated mechanisms that floorplan standard cells composed of devices or higher-level units composed of cells for the balanced current or reliability of C4 bumps.
There are dynamic management mechanisms used in other areas such as power or temperature, but none for current management. Such existing mechanisms may indirectly control the exposure to excessive current delivery, but they cannot directly keep C4 current to be met the limit.
In addition, dynamic current management mechanisms can be coupled with static design methodologies such as C4 current-aware floorplanning and C4 placement optimization in order to improve current delivery into a chip as well as performance.